1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) for establishing system synchronization between a transmitter and a receiver, and more particularly to a phase-locked loop for maintaining system synchronization of a receiver with a transmitter through packet dropout in a wireless communications system of packet transmission.
2. Description of the Background Art
Recently, a transmitter and a receiver included in a packet transmission system for implementing wireless communication have come into use. The receiver establishes system synchronization based on the system timing information contained in a packet transmitted from the transmitter. The transmitter assembles a transmission packet having its length, transmission interval and format regulated all the time. The receiver is responsive to system timing information incoming periodically on a packet to restore the operating timing of the transmitter to establish synchronization with the transmitter. A phase-locked loop for establishing such system synchronization is disclosed in, for example, Japanese Patent No. 3159981.
With the above-described conventional system, in which the operational timing on the receiver is defined by system timing information periodically supplied, it is essential that the system timing information is always received. Hence, if optimal wireless network circumstances cannot be secured to interrupt consecutive packet reception, then so-called packet dropout may be caused to give rise to a void in the timing information so as to raise a serious error in the correction information for recovering timing, with the result that it may become necessary to re-establish the system synchronization from the outset. Such re-synchronization would cause the system synchronization to be once marred critically.
In the phase-locked loop, if a period of time in which the phase-locked loop cannot trace the timing is so long as to cause packet dropout and thereafter the system information is recovered, then error in temporal position is cumulatively increased of the clock for receiver system operation with respect to the system timing information. In an attempt to recover the system synchronization, if the frequency of the clock for receiver system operation is corrected, then the increased cumulative error would cause the frequency of the clock for receiver system operation to drastically be shifted, thus destabilizing the system synchronization.
On the other hand, if the clock frequency of a clock on the receiver circuitry, detecting the system timing information, is not synchronous with the frequency of the clock for receiver system operation, which is in operation under system synchronization, both frequencies are also not synchronous with the clock used for generating the system timing information on the transmitter. The clock for receiver system operation and the clock used for generating system timing information may hereinafter be referred to as a clock for receiver system operation and a clock for transmitter system operation, respectively. It is thus required to use those three clock frequencies, not synchronous with each other, to establish system synchronization for synchronizing the frequency of the clock for receiver system operation with the frequency of the clock for transmitter system operation.
Heretofore, if an acoustic system is to be incorporated into a communications system, it has been necessary to design the acoustic system based upon the communications system or vice versa. In case any existing communications and acoustic systems are to be utilized without modification, a third frequency, such as voice signal sampling frequency, has to be used for system designing. The conventional phase-locked loop is, however, not up to this request.